Most wireless receiver circuits employ similar architectures. On the transmitter side (not shown), digital user data (which may be encoded or sampled voice data) is input to a bit-symbol encoder, which may be implemented as a dedicated circuit or a combination of hardware and software (such as a DSP). In any event, the bit-symbol encoder typically splits the data into two half-rate streams. These streams are modulated onto a pair of orthogonal carriers, called I and Q for in-phase and quadrature-phase carriers respectively, although other modulation schemes are known. This is a 2-D (or two-dimensional) transmission scheme. The I and Q signals are combined for transmission over an RE channel as is well known in the art.
Referring now to FIG. 1, a typical wireless receiver circuit 10 has an RF antenna 12 to receive an incident RF signal. The RF signal from the antenna may be subjected to a band pre-select filter (not shown), and typically is input to a low-noise amplifier 14 (LNA). The filtered, amplified RF signal is input to a first mixer 16, to bring the RF signal down to a selected intermediate frequency (IF). Mixer 16 is driven by a first local oscillator signal LO1 applying techniques that are well known in the radio prior art.
An IF amplifier 18 and/or low pass filter (not shown) further conditions the signal, which is then split into two paths. The IF signal is input to a second mixer 20 and also input to a third mixer 24. The second mixer 20 is driven by a second local oscillator signal LO2, arranged to recover or demodulate the in-phase baseband analog signal “i”. The local oscillator signal LO2 is also input to a 90-degree delay or phase shifter 22, the output of which drives the third mixer 24. The IF signal is input to the third mixer as illustrated, so that the third mixer 24 demodulates the quadrature-phase orthogonal baseband analog signal “q”. In this description, we use lower case “i” and “q” to refer to the analog signals corresponding to the I and Q digital data streams, respectively.
Next the in-phase analog signal “i” is input to a low pass filter 30, and then to a buffer 32. The buffered signal is input to an analog-to-digital converter circuit (“ADC”) 34 for conversion into digital data. This stage recovers, at node 35, one of the pair of half-rate data streams originally encoded in the transmitter.
Similarly, the quadrature phase signal “q” recovered by the third mixer 24 is filtered in LPF 40 and buffer 42. The resulting analog signal is input to a second analog to digital converter circuit 44 (ADC) for conversion into digital data. This stage recovers, at node 45, the other one of the pair of half-rate data streams originally encoded in the transmitter. Both ADC's are driven by a common receive clock signal 48 (“RX clock”), which may have a frequency of, for example, 44 MHz. The two ADCs are thus synchronized; they operated on the i and q signals in parallel. The recovered digital data streams are further processed in a pair of FIR low-pass filters LPF 36, 46 respectively. The two digital streams are then further processed by other functional blocks such as a complex equalizer and correlators as is known in the art.
Various ADC circuits are known that could be used in this architecture. They include the conventional feedback-type ADC, which is small but slow. U.S. Pat. No. 5,229,771 to Hanlon describes an integrating type of ADC circuit in which switches, like multiplexers, are used to select various reference voltages Vref+, Vref− and trip voltages Vtrip(n) etc. for use in the integration stage of the ADC; but that system still converts only a single analog input signal Vin during a cycle.
A faster approach is realized in a parallel or “flash” ADC. A flash ADC incorporates a plurality of comparators arranged in parallel, so as to form the N-bit digital output signal in a single cycle. U.S. Pat. No. 6,169,504 describes the use of interleaved sampling for faster conversion in the context of a parallel series of comparators. Improved accuracy can be obtained by using pipelined ADC circuits. These too are known, as described for example in U.S. Pat. No. 6,166,675.
One significant drawback of the receiver architecture summarized above is related to the pair of ADC circuits. Mismatches in the internal comparators of the ADCs must be carefully controlled to minimize errors. Especially in pipelined converter designs, offset, gain errors and other imperfections in the ADC circuits add to their complexity. See U.S. Pat. No. 5,594,445. Consequently, high performance ADC circuits are expensive both in terms of chip area and power consumption. These factors are of paramount importance in integrated circuit designs for portable applications such as cell phones, pagers and other wireless communication equipment.
Accordingly, it would be advantageous to reduce the amount of chip area that must be dedicated to ADC circuits in a receiver. It would also be advantageous to reduce the number of ADC circuits required in a receiver, without sacrificing speed or accuracy of received data recovery.